Issued Patents 2016
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9524363 | Element placement in circuit design based on preferred location | Charles J. Alpert, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan | 2016-12-20 |
| 9417945 | Error checking and correction for NAND flash devices | Shawn P. Authement, Jente B. Kuang | 2016-08-16 |
| 9418190 | Virtual sub-net based routing | Sven Peyer, Ronald D. Rose, Sourav Saha | 2016-08-16 |
| 9298872 | Apportioning synthesis effort for better timing closure | Thomas E. Rosser, Manikandan Viswanath | 2016-03-29 |
| 9245084 | Virtual sub-net based routing | Sven Peyer, Ronald D. Rose, Sourav Saha | 2016-01-26 |