EN

Eric Naviasky

CS Cadence Design Systems: 5 patents #5 of 202Top 3%
Overall (2016): #29,097 of 481,213Top 7%
5
Patents 2016

Issued Patents 2016

Showing 1–5 of 5 patents

Patent #TitleCo-InventorsDate
9490795 System and method for selectively coupled parasitic compensation for input referred voltage offset in electronic circuit Ali Ulas Ilhan 2016-11-08
9450511 Differential signal detector and full wave rectifier circuit thereof with common mode signal rejection Santiago Luis Bortman 2016-09-20
9405314 System and method for synchronously adjusted delay and distortion mitigated recovery of signals Thomas Evan Wilson 2016-08-02
9356767 Hybrid analog/digital clock recovery system Ali Ulas Ilhan 2016-05-31
9285778 Time to digital converter with successive approximation architecture William P. Evans, Anthony Caviglia 2016-03-15