Issued Patents 2016
Showing 25 most recent of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529598 | Transaction abort instruction | Dan F. Greiner, Marcel Mitran, Timothy J. Slegel | 2016-12-27 |
| 9524205 | Code fingerprint-based processor malfunction detection | Giles R. Frazier, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum | 2016-12-20 |
| 9507602 | Sharing program interrupt logic in a multithreaded processor | Khary J. Alexander, Michael Billeci, Fadi Y. Busaba, Mark S. Farrell, Timothy J. Slegel | 2016-11-29 |
| 9495138 | Scheme for verifying the effects of program optimizations | Giles R. Frazier, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum | 2016-11-15 |
| 9495157 | Fingerprint-based branch prediction | Jonathan D. Bradbury, Giles R. Frazier, Michael K. Gschwind, Anthony Saporito, Chung-Lung K. Shum | 2016-11-15 |
| 9495225 | Parallel execution mechanism and operating method thereof | Marcel Mitran, Moriyoshi Ohara | 2016-11-15 |
| 9495306 | Dynamic management of a processor state with transient cache memory | Jonathan D. Bradbury, Dan F. Greiner, Michael K. Gschwind, Younes Manton, Anthony Saporito +3 more | 2016-11-15 |
| 9483409 | Store forwarding cache | Khary J. Alexander, Jonathan T. Hsieh, James R. Mitchell | 2016-11-01 |
| 9477514 | Transaction begin/end instructions | Dan F. Greiner, Marcel Mitran, Timothy J. Slegel | 2016-10-25 |
| 9471504 | Store forwarding cache | Khary J. Alexander, Jonathan T. Hsieh, James R. Mitchell | 2016-10-18 |
| 9471312 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2016-10-18 |
| 9459875 | Dynamic enablement of multithreading | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +5 more | 2016-10-04 |
| 9459867 | Instruction to load data up to a specified memory boundary indicated by the instruction | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2016-10-04 |
| 9460023 | Storing a system-absolute address (SAA) in a first level translation look-aside buffer (TLB) | Khary J. Alexander, Jonathan T. Hsieh, Timothy J. Slegel | 2016-10-04 |
| 9459868 | Instruction to load data up to a dynamically determined memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2016-10-04 |
| 9454370 | Conditional transaction end instruction | Dan F. Greiner, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2016-09-27 |
| 9454377 | Speculative branch handling for transaction abort | Michael Billeci, James J. Bonanno, Adam B. Collura, Anthony Saporito, Timothy Siegel | 2016-09-27 |
| 9455742 | Compression ratio for a compression engine | Thomas Fuchs, Anthony T. Sofia, Joerg-Stephan Vogt | 2016-09-27 |
| 9448797 | Restricted instructions in transactional execution | Dan F. Greiner, Timothy J. Slegel | 2016-09-20 |
| 9448796 | Restricted instructions in transactional execution | Dan F. Greiner, Timothy J. Slegel | 2016-09-20 |
| 9442737 | Restricting processing within a processor to facilitate transaction completion | Khary J. Alexander, Brenton F. Belmar, Randall W. Philley, Anthony Saporito, Timothy J. Slegel | 2016-09-13 |
| 9442738 | Restricting processing within a processor to facilitate transaction completion | Khary J. Alexander, Brenton F. Belmar, Randall W. Philley, Anthony Saporito, Timothy J. Slegel | 2016-09-13 |
| 9436477 | Transaction abort instruction | Dan F. Greiner, Marcel Mitran, Timothy J. Slegel | 2016-09-06 |
| 9430235 | Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors | Gregory W. Alexander, Khary J. Alexander, Brian W. Curran, Jonathan T. Hsieh, James R. Mitchell +2 more | 2016-08-30 |
| 9424012 | Programmable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Chung-Lung K. Shum | 2016-08-23 |