AS

Ankush Sood

CS Cadence Design Systems: 2 patents #18 of 202Top 9%
Overall (2016): #159,298 of 481,213Top 35%
2
Patents 2016

Issued Patents 2016

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
9411912 Clock topology planning for reduced power consumption Aaron Paul Hurst 2016-08-09
9280614 Methods, systems, and apparatus for clock topology planning with reduced power consumption Aaron Paul Hurst 2016-03-08