Issued Patents 2016
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9329869 | Prefix computer instruction for compatibily extending instruction functionality | Michael K. Gschwind | 2016-05-03 |
| 9329946 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2016-05-03 |
| 9329890 | Managing high-coherence-miss cache lines in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-05-03 |
| 9329850 | Relocation of instructions that use relative addressing | Michael K. Gschwind | 2016-05-03 |
| 9323530 | Caching optimized internal instructions in loop buffer | Michael K. Gschwind | 2016-04-26 |
| 9325703 | Automatic security parameter management and renewal | Ashish Kundu, Ruchi Mahindru, Ajay Mohindra, Mahesh Viswanathan | 2016-04-26 |
| 9317379 | Using transactional execution for reliability and recovery of transient failures | Michael K. Gschwind | 2016-04-19 |
| 9311093 | Prefix computer instruction for compatibly extending instruction functionality | Michael K. Gschwind | 2016-04-12 |
| 9311228 | Power reduction in server memory system | David M. Daly, Tejas Karkhanis | 2016-04-12 |
| 9311178 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Eric M. Schwarz | 2016-04-12 |
| 9311095 | Using register last use information to perform decode time computer instruction optimization | Michael K. Gschwind | 2016-04-12 |
| 9304935 | Enhancing reliability of transaction execution by using transaction digests | Michael K. Gschwind | 2016-04-05 |
| 9298623 | Identifying high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-03-29 |
| 9298626 | Managing high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-03-29 |
| 9298464 | Instruction merging optimization | Michael K. Gschwind | 2016-03-29 |
| 9292291 | Instruction merging optimization | Michael K. Gschwind | 2016-03-22 |
| 9292444 | Multi-granular cache management in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz +1 more | 2016-03-22 |
| 9292357 | Software enabled and disabled coalescing of memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2016-03-22 |
| 9292337 | Software enabled and disabled coalescing of memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2016-03-22 |
| 9292289 | Enhancing reliability of transaction execution by using transaction digests | Michael K. Gschwind | 2016-03-22 |
| 9286067 | Method and apparatus for a hierarchical synchronization barrier in a multi-node system | Robert W. Wisniewski | 2016-03-15 |
| 9286072 | Using register last use infomation to perform decode-time computer instruction optimization | Michael K. Gschwind | 2016-03-15 |
| 9262343 | Transactional processing based upon run-time conditions | Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Chung-Lung K. Shum | 2016-02-16 |
| 9244781 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2016-01-26 |
| 9244782 | Salvaging hardware transactions | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2016-01-26 |