| 9507599 |
Instruction set architecture with extensible register addressing |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-11-29 |
| 9501279 |
Local instruction loop buffer utilizing execution unit register file |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-11-22 |
| 9465613 |
Instruction predication using unused datapath facilities |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-10-11 |
| 9405536 |
Floating point execution unit for calculating packed sum of absolute differences |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-08-02 |
| 9405535 |
Floating point execution unit for calculating packed sum of absolute differences |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-08-02 |
| 9378168 |
Shared receive queue allocation for network on a chip communication |
Jeffrey Douglas Brown |
2016-06-28 |
| 9354887 |
Instruction buffer bypass of target instruction in response to partial flush |
Eric O. Mejdrich, Paul E. Schardt, Matthew R. Tubbs |
2016-05-31 |
| 9354884 |
Processor with hybrid pipeline capable of operating in out-of-order and in-order modes |
Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Ken V. Vu +1 more |
2016-05-31 |
| 9342309 |
Extensible execution unit interface architecture with multiple decode logic and multiple execution units |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-05-17 |
| 9329870 |
Extensible execution unit interface architecture with multiple decode logic and multiple execution units |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-05-03 |
| 9317291 |
Local instruction loop buffer utilizing execution unit register file |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-04-19 |
| 9317294 |
Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-04-19 |
| 9311096 |
Local instruction loop buffer utilizing execution unit register file |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-04-12 |
| 9311090 |
Indirect instruction predication |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-04-12 |
| 9304771 |
Indirect instruction predication |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-04-05 |
| 9292290 |
Instruction set architecture with opcode lookup using memory attribute |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-03-22 |
| 9292965 |
Accelerated data structure positioning based upon view orientation |
David Keith Fowler, Eric O. Mejdrich, Paul E. Schardt |
2016-03-22 |
| 9286071 |
Instruction set architecture with opcode lookup using memory attribute |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-03-15 |
| 9274591 |
General purpose processing unit with low power digital signal processing (DSP) mode |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-03-01 |
| 9256574 |
Dynamic thread status retrieval using inter-thread communication |
Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt |
2016-02-09 |
| 9256573 |
Dynamic thread status retrieval using inter-thread communication |
Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt |
2016-02-09 |
| 9251116 |
Direct interthread communication dataport pack/unpack and load/save |
Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs |
2016-02-02 |
| 9244840 |
Cache swizzle with inline transposition |
Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt |
2016-01-26 |
| 9239791 |
Cache swizzle with inline transposition |
Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt |
2016-01-19 |
