LH

Lisa C. Heller

IBM: 15 patents #192 of 10,295Top 2%
Overall (2016): #2,742 of 481,213Top 1%
15
Patents 2016

Issued Patents 2016

Patent #TitleCo-InventorsDate
9459875 Dynamic enablement of multithreading Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +5 more 2016-10-04
9454490 Invalidating a range of two or more translation table entries and instruction therefore Timothy J. Slegel, Erwin Pfeffer, Kenneth E. Plambeck 2016-09-27
9454372 Thread context restoration in a multithreading computer system Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more 2016-09-27
9449314 Virtualization of a central processing unit measurement facility Patrick M. West, Jr., Phil C. Yeh 2016-09-20
9417876 Thread context restoration in a multithreading computer system Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more 2016-08-16
9389897 Exiting multiple threads of a simulation environment in a computer Fadi Y. Busaba, Mark S. Farrell, Michael P. Mullen 2016-07-12
9378128 Dynamic address translation with fetch protection in an emulated environment Dan F. Greiner, Charles W. Gainey, Jr., Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel +1 more 2016-06-28
9372805 Operating on translation look-aside buffers in a multiprocessor environment Norbert Hagspiel, Ute Gaertner, Hanno Ulrich, Rebecca S. Wisniewski 2016-06-21
9354873 Performing a clear operation absent host intervention Charles W. Gainey, Jr., Dan F. Greiner, Damian L. Osisek, Gustav E. Sittmann, III 2016-05-31
9354883 Dynamic enablement of multithreading Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +5 more 2016-05-31
9330018 Suppressing virtual address translation utilizing bits and instruction tagging Joerg Deutschle, Ute Gaertner 2016-05-03
9330017 Suppressing virtual address translation utilizing bits and instruction tagging Joerg Deutschle, Ute Gaertner 2016-05-03
9323640 Method and system for measuring the performance of a computer system on a per logical partition basis Jane H. Bartik, Michael Billeci, Donald G. O'Brien, Bruce Wagar, Patrick M. West, Jr. 2016-04-26
9251085 Performing a clear operation absent host intervention Charles W. Gainey, Jr., Dan F. Greiner, Damian L. Osisek, Gustav E. Sittmann, III 2016-02-02
9244856 Dynamic address translation with translation table entry format control for identifying format of the translation table entry Dan F. Greiner, Damian L. Osisek, Erwin Pfeffer, Timothy Siegel, Charles F. Webb 2016-01-26