SG

Sandipan Ghosh

CS Cadence Design Systems: 1 patents #48 of 202Top 25%
📍 New Delhi, CA: #9 of 18 inventorsTop 50%
Overall (2016): #240,588 of 481,213Top 50%
1
Patents 2016

Issued Patents 2016

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9305133 System and method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor Anjna Khanna 2016-04-05