SB

Sandeep Brahmadathan

CS Cadence Design Systems: 1 patents #48 of 202Top 25%
🗺 California: #22,912 of 57,791 inventorsTop 40%
Overall (2016): #241,247 of 481,213Top 55%
1
Patents 2016

Issued Patents 2016

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9471094 Method of aligning timing of a chip select signal with a cycle of a memory device Jeffrey Earl, Todd Barth 2016-10-18