Issued Patents 2011
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8072003 | Integrated circuit device and associated layout including two pairs of co-aligned complementary gate electrodes with offset gate contact structures | Michael C. Smayling | 2011-12-06 |
| 8058691 | Semiconductor device including cross-coupled transistors formed from linear-shaped gate level features | — | 2011-11-15 |
| 8058671 | Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch | Michael C. Smayling | 2011-11-15 |
| 8035133 | Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitch | Michael C. Smayling | 2011-10-11 |
| 8030689 | Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segment | Michael C. Smayling | 2011-10-04 |
| 8022441 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level | Michael C. Smayling | 2011-09-20 |
| 7994545 | Methods, structures, and designs for self-aligning local interconnects used in integrated circuits | Michael C. Smayling | 2011-08-09 |
| 7989848 | Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or ground | Michael C. Smayling | 2011-08-02 |
| 7989847 | Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengths | Michael C. Smayling | 2011-08-02 |
| 7956421 | Cross-coupled transistor layouts in restricted gate level layout architecture | — | 2011-06-07 |
| 7952119 | Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitch | Michael C. Smayling | 2011-05-31 |
| 7948013 | Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch | Michael C. Smayling | 2011-05-24 |
| 7948012 | Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment | Michael C. Smayling | 2011-05-24 |
| 7943967 | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments | Michael C. Smayling | 2011-05-17 |
| 7943966 | Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segment | Michael C. Smayling | 2011-05-17 |
| 7939443 | Methods for multi-wire routing and apparatus implementing same | Daryl Fox | 2011-05-10 |
| 7939898 | Diffusion variability control and transistor device sizing using threshold voltage implant | Michael C. Smayling | 2011-05-10 |
| 7932545 | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers | Michael C. Smayling | 2011-04-26 |
| 7932544 | Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions | Michael C. Smayling | 2011-04-26 |
| 7923757 | Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level | Michael C. Smayling | 2011-04-12 |
| 7917885 | Methods for creating primitive constructed standard cells | — | 2011-03-29 |
| 7917879 | Semiconductor device with dynamic array section | Michael C. Smayling | 2011-03-29 |
| 7910959 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level | Michael C. Smayling | 2011-03-22 |
| 7910958 | Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment | Michael C. Smayling | 2011-03-22 |
| 7906801 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions | Michael C. Smayling | 2011-03-15 |