Issued Patents 2011
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8069379 | Memory system with point-to-point request interconnect | Richard E. Perego | 2011-11-29 |
| 8068357 | Memory controller with multi-modal reference pad | John Wilson, John Eble, Jade M. Kizer, Lei Luo, John W. Poulton +1 more | 2011-11-29 |
| 8059476 | Control component for controlling a delay interval within a memory component | Ely Tsern, Craig E. Hampel, Donald C. Stark | 2011-11-15 |
| 8054707 | Low energy memory component | — | 2011-11-08 |
| 8050134 | Multi-column addressing mode memory system including an integrated circuit memory device | Lawrence Lai, Chad A. Bellows, Wayne S. Richardson | 2011-11-01 |
| 8045407 | Memory-write timing calibration including generation of multiple delayed timing signals | — | 2011-10-25 |
| 8028144 | Memory module with reduced access granularity | Craig E. Hampel | 2011-09-27 |
| 8019958 | Memory write signaling and methods thereof | Richard M. Barth, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2011-09-13 |
| 7989265 | Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device | Ely Tsern, Ian Shaeffer | 2011-08-02 |
| 7962715 | Memory controller for non-homogeneous memory system | — | 2011-06-14 |
| 7961532 | Bimodal memory controller | — | 2011-06-14 |
| 7948812 | Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift | — | 2011-05-24 |
| 7925808 | Memory system and device with serialized data transfer | Richard E. Perego | 2011-04-12 |
| 7921245 | Memory system and device with serialized data transfer | Richard E. Perego | 2011-04-05 |
| 7921236 | Method and apparatus for simultaneous bidirectional signaling in a bus topology | — | 2011-04-05 |
| 7916570 | Low power memory device | Ely Tsern, Craig E. Hampel | 2011-03-29 |
| 7907470 | Multi-column addressing mode memory system including an integrated circuit memory device | Lawrence Lai, Chad A. Bellows, Wayne S. Richardson | 2011-03-15 |
| 7882423 | Unidirectional error code transfer for both read and write data transmitted via bidirectional data link | Yuanlong Wang | 2011-02-01 |
| 7870357 | Memory system and method for two step memory write operations | Paul G. Davis, Craig E. Hampel | 2011-01-11 |