Issued Patents 2011
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7917882 | Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof | Soumya Banerjee, Thomas Stephen Chanak, Jr. | 2011-03-29 |