Issued Patents 2011
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8060847 | Clock model for formal verification of a digital circuit description | James Andrew Garrard Seawright, Jeremy Rutledge Levitt | 2011-11-15 |
| 7890897 | Measure of analysis performed in property checking | Jeremy Rutledge Levitt, Chian-min Richard Ho, Ping Fai Yeung, Kalyana C. Mulam, Ramesh Sathianathan | 2011-02-15 |