Issued Patents 2011
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7996625 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture | Manoj Khare, Faye A. Briggs, Lily P. Looi, Kai Cheng | 2011-08-09 |
| 7991875 | Link level retry scheme | Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Phanindra Kumar Mannava, Rajee Ram +3 more | 2011-08-02 |