Issued Patents 2011
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8015358 | System bus structure for large L2 cache array topology with different latency domains | Vicente Enrique Chung, Guy L. Guthrie, Jeffrey A. Stuecheli | 2011-09-06 |
| 8001330 | L2 cache controller with slice directory and unified cache structure | Leo James Clark, James Stephen Fields, Jr., Guy L. Guthrie | 2011-08-16 |
| 7996564 | Remote asynchronous data mover | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Ronald Nick Kalla, Ramakrishnan Rajamony, Balaram Sinharoy +1 more | 2011-08-09 |
| 7992051 | Method, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracing | Ra'ed Mohammad Al-Omari, Alexander Erik Mericas | 2011-08-02 |
| 7987320 | Cache mechanism and method for avoiding cast out on bad victim select and recycling victim select operation | Robert H. Bell, Jr., Guy L. Guthrie | 2011-07-26 |
| 7966454 | Issuing global shared memory operations via direct cache injection to a host fabric interface | Lakshimarayana B. Arimilli, Ravi Kumar Arimilli, Robert S. Blackmore, Chulho Kim, Ramakrishnan Rajamony +1 more | 2011-06-21 |
| 7944932 | Interconnect fabric for a data processing system | Leo James Clark, James Stephen Fields, Jr., Guy L. Guthrie | 2011-05-17 |
| 7941611 | Filtering snooped operations | Benjiman L. Goodman, Guy L. Guthrie, Derek E. Williams | 2011-05-10 |
| 7925842 | Allocating a global shared memory | Ravi Kumar Arimilli, Robert S. Blackmore, Ramakrishnan Rajamony | 2011-04-12 |
| 7917730 | Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller | Charles F. Marino, John T. Holloway, Praveen S. Reddy | 2011-03-29 |
| 7913123 | Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers | Ra'ed Mohammad Al-Omari, Alexander Erik Mericas | 2011-03-22 |
| 7890704 | Implementing an enhanced hover state with active prefetches | Leo James Clark, James Stephen Fields, Jr., Pak-kin Mak | 2011-02-15 |
| 7865650 | Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements | Charles F. Marino, John T. Holloway, Praveen S. Reddy | 2011-01-04 |