VS

Vinaya Kumar Singh

CS Cadence Design Systems: 1 patents #62 of 259Top 25%
📍 Noida, IN: #7 of 40 inventorsTop 20%
Overall (2011): #135,587 of 364,097Top 40%
1
Patents 2011

Issued Patents 2011

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7984401 Method for checking a status of a signal port to identify an over-constrained event Amir Lehavot, Joezac John Zachariah, Jose Barandiaran, Axel Scherer 2011-07-19