Issued Patents 2011
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8004888 | Flash mirror bit architecture using single program and erase entity as logical cell | — | 2011-08-23 |
| 7907455 | High VT state used as erase condition in trap based nor flash cell design | — | 2011-03-15 |
| 7881105 | Quad+bit storage in trap based flash design using single program and erase entity as logical cell | — | 2011-02-01 |
| 7864596 | Sector configure registers for a flash device generating multiple virtual ground decoding schemes | — | 2011-01-04 |