Issued Patents 2004
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6826652 | Smart cache | Gerard Chauvel, Dominique D'Inverno | 2004-11-30 |
| 6792508 | Cache with multiple fill modes | Gerard Chauvel, Dominique D'Inverno | 2004-09-14 |
| 6789172 | Cache and DMA with a global valid bit | Gerard Chauvel | 2004-09-07 |
| 6772326 | Interruptible an re-entrant cache clean range instruction | Gerard Chauvel, Dominique D'Inverno | 2004-08-03 |
| 6766421 | Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier field | Gerard Chauvel | 2004-07-20 |
| 6760829 | MMU descriptor having big/little endian bit to control the transfer data between devices | Gerard Chauvel, Dominique D'Inverno | 2004-07-06 |
| 6754781 | Cache with DMA and dirty bits | Gerard Chauvel | 2004-06-22 |
| 6751706 | Multiple microprocessors with a shared cache | Gerard Chauvel, Maija Kuusela, Dominique D'Inverno | 2004-06-15 |
| 6745293 | Level 2 smartcache architecture supporting simultaneous multiprocessor accesses | Gerard Chauvel | 2004-06-01 |
| 6742104 | Master/slave processing system with shared translation lookaside buffer | Gerard Chauvel, Dominique D'Inverno | 2004-05-25 |
| 6742103 | Processing system with shared translation lookaside buffer | Gerard Chauvel, Dominique D'Inverno | 2004-05-25 |
| 6728838 | Cache operation based on range of addresses | Gerard Chauvel | 2004-04-27 |
| 6697916 | Cache with block prefetch and DMA | Gerard Chauvel | 2004-02-24 |
| 6684280 | Task based priority arbitration | Gerard Chauvel | 2004-01-27 |
| 6681297 | Software controlled cache configuration based on average miss rate | Gerard Chauvel, Dominique D'Inverno | 2004-01-20 |
| 6678797 | Cache/smartcache with interruptible block prefetch | Gerard Chauvel | 2004-01-13 |