Issued Patents 2004
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6801985 | Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses | Joseph Zbiciak | 2004-10-05 |
| 6694385 | Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor | Charles Fuoco, Sanjive Agarwala | 2004-02-17 |
| 6681270 | Effective channel priority processing for transfer controller with hub and ports | Sanjive Agarwala, Iain Robertson | 2004-01-20 |