Issued Patents 2004
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833568 | Geometry-controllable design blocks of MOS transistors for improved ESD protection | Kwang-Hoon Oh | 2004-12-21 |
| 6826026 | Output buffer and I/O protection circuit for CMOS technology | Roger A. Cline | 2004-11-30 |
| 6804095 | Drain-extended MOS ESD protection structure | Keith E. Kunz, Dan M. Mosher | 2004-10-12 |
| 6781204 | Spreading the power dissipation in MOS transistors for improved ESD protection | Kwang-Hoon Oh | 2004-08-24 |
| 6764892 | Device and method of low voltage SCR protection for high voltage failsafe ESD applications | Keith E. Kunz, Hisashi Shichijo | 2004-07-20 |
| 6690066 | Minimization and linearization of ESD parasitic capacitance in integrated circuits | Heng-Chih Lin, Baher Haroun | 2004-02-10 |