Issued Patents 2004
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6807646 | System and method for time slicing deterministic patterns for reseeding in logic built-in self-test | Thomas W. Williams, Peter Wohl, John A. Waicukauski | 2004-10-19 |
| 6766501 | System and method for high-level test planning for layout | Suryanarayana Duggirala, Thomas W. Williams | 2004-07-20 |