Issued Patents 2004
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6812541 | Integrated circuit with a reduced risk of punch-through between buried layers, and fabrication process | — | 2004-11-02 |
| 6756279 | Method for manufacturing a bipolar transistor in a CMOS integrated circuit | Herve Jaouen, Guillaume Bouche | 2004-06-29 |
| 6673703 | Method of fabricating an integrated circuit | Herve Jaouen | 2004-01-06 |