KI

Kevin R. Iadonato

SE Seiko Epson: 2 patents #174 of 889Top 20%
HS Hitachi Micro Systems: 1 patents #1 of 5Top 20%
📍 San Jose, CA: #245 of 2,805 inventorsTop 9%
🗺 California: #2,168 of 28,370 inventorsTop 8%
Overall (2004): #25,748 of 270,089Top 10%
3
Patents 2004

Issued Patents 2004

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
6782521 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip Le Trong Nguyen 2004-08-24
6772327 Floating point unit pipeline synchronized with processor pipeline Prasenjit Biswas, Gautam Dewan, Norio Nakagawa, Kunio Uchiyama 2004-08-03
6757808 System and method for assigning tags to control instruction processing in a superscalar processor Trevor Deosaran, Sanjiv Garg 2004-06-29