Issued Patents 2004
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6822903 | Apparatus and method for disturb-free programming of passive element memory cells | N. Johan Knall | 2004-11-23 |
| 6816431 | Magnetic random access memory using memory cells with rotated magnetic storage elements | Yu Lu, William Robert Reohr | 2004-11-09 |
| 6816410 | Method for programming a three-dimensional memory array incorporating serial chain diode stack | Bendik Kleveland | 2004-11-09 |
| 6807119 | Array containing charge storage and dummy transistors and method of operating the array | Luca Fasoli, Alper Ilkbahar | 2004-10-19 |
| 6781878 | Dynamic sub-array group selection scheme | Bendik Kleveland | 2004-08-24 |
| 6778431 | Architecture for high-speed magnetic memories | Dietmar Gogl, William Robert Reohr | 2004-08-17 |
| 6768685 | Integrated circuit memory array with fast test mode utilizing multiple word line selection and method therefor | — | 2004-07-27 |
| 6765813 | Integrated systems using vertically-stacked three-dimensional memory cells | J. James Tringali, Colm P. Lysaght, Alper Ilkbahar, Christopher S. Moore, David Friedman | 2004-07-20 |
| 6754102 | Method for programming a three-dimensional memory array incorporating serial chain diode stack | Bendik Kleveland | 2004-06-22 |
| 6737675 | High density 3D rail stack arrays | Kedar Patel, Alper Ilkbahar, Andrew J. Walker | 2004-05-18 |
| 6735546 | Memory device and method for temperature-based control over write and/or read operations | — | 2004-05-11 |
| 6735104 | Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays | — | 2004-05-11 |
| 6724665 | Memory device and method for selectable sub-array activation | Bendik Kleveland | 2004-04-20 |
| 6711043 | Three-dimensional memory cache system | David Friedman, J. James Tringali, James Schneider, Christopher S. Moore, Daniel C. Steere | 2004-03-23 |