Issued Patents 2004
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6819619 | Semiconductor memory device allowing reduction of an area loss | Hiroshi Kato | 2004-11-16 |
| 6781431 | Clock generating circuit | Yasuhiko Taito, Akira Yamazaki, Nobuyuki Fujii, Mihoko Akiyama, Mako Okamoto | 2004-08-24 |
| 6777707 | Semiconductor integrated circuit with voltage down converter adaptable for burn-in testing | Mihoko Akiyama, Akira Yamazaki, Yasuhiko Taito, Nobuyuki Fujii, Mako Okamoto | 2004-08-17 |
| 6768354 | Multi-power semiconductor integrated circuit device | Akira Yamazaki, Yasuhiko Taito, Nobuyuki Fujii, Mihoko Akiyama, Mako Kobayashi | 2004-07-27 |
| 6704231 | Semiconductor memory device with circuit executing burn-in testing | Mitsuya Kinoshita | 2004-03-09 |
| 6700434 | Substrate bias voltage generating circuit | Nobuyuki Fujii, Mihoko Akiyama, Akira Yamazaki, Mako Kobayashi, Yasuhiko Taito | 2004-03-02 |