Issued Patents 2004
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6835981 | Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions | Takashi Yamada, Hajime Nagano, Ichiro Mizushima, Tsutomu Sato, Shinichi Nitta | 2004-12-28 |
| 6833301 | Semiconductor device with an improved gate electrode pattern and a method of manufacturing the same | — | 2004-12-21 |
| 6828222 | Method for manufacturing multilayer wiring structure semiconductor device | — | 2004-12-07 |
| 6815280 | Method of manufacturing a semiconductor device including a plurality of kinds of MOS transistors having different gate widths | — | 2004-11-09 |
| 6768182 | Semiconductor device | — | 2004-07-27 |
| 6734506 | Semiconductor device including a plurality of kinds of MOS transistors having different gate widths and method of manufacturing the same | — | 2004-05-11 |
| 6724046 | Semiconductor device having patterned SOI structure and method for fabricating the same | — | 2004-04-20 |