Issued Patents 2004
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6829673 | Latched address multi-chunk write to EEPROM | Douglas J. Lee, Mehrdad Mofidi, Sanjay Mehrotra | 2004-12-07 |
| 6822911 | Dynamic column block selection | — | 2004-11-23 |
| 6801454 | Voltage generation circuitry having temperature compensation | Yongliang Wang, Chi-Ming Wang | 2004-10-05 |
| 6795349 | Method and system for efficiently reading and programming of dual cell memory elements | — | 2004-09-21 |
| 6781877 | Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells | Khandker N. Quader, Yan Li, Jian Chen, Yupin Fong | 2004-08-24 |
| 6771536 | Operating techniques for reducing program and read disturbs of a non-volatile memory | Yan Li, Jian Chen | 2004-08-03 |
| 6741502 | Background operation for memory cells | — | 2004-05-25 |