VN

Veerapaneni Nagbhushan

IN Intel: 1 patents #813 of 2,313Top 40%
📍 Saratoga, CA: #143 of 387 inventorsTop 40%
🗺 California: #8,555 of 28,370 inventorsTop 35%
Overall (2004): #93,204 of 270,089Top 35%
1
Patents 2004

Issued Patents 2004

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6757878 Method and apparatus for layout synthesis of regular structures using relative placement Vinoo N. Srinivasan, Kumar Lalgudi 2004-06-29