Issued Patents 2004
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6815775 | ESD protection design with turn-on restraining method and structures | Jeng-Jie Peng, Hsin-Chin Jiang | 2004-11-09 |
| 6806160 | Method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process | Chyh-Yih Chang, Tien-Hao Tang | 2004-10-19 |
| 6768619 | Low-voltage-triggered SOI-SCR device and associated ESD protection circuit | Kei-Kang Hung, Shao-Chang Huang | 2004-07-27 |
| 6765771 | SCR devices with deep-N-well structure for on-chip ESD protection circuits | Hun-Hsien Chang, Wen-Tai Wang | 2004-07-20 |
| 6750517 | Device layout to improve ESD robustness in deep submicron CMOS technology | Mau-Lin Wu | 2004-06-15 |
| 6750515 | SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection | Kei-Kang Hung, Chyh-Yih Chang | 2004-06-15 |
| 6747861 | Electrostatic discharge protection for a mixed-voltage device using a stacked-transistor-triggered silicon controlled rectifier | Chien-Hui Chung, Hsin-Chin Jiang | 2004-06-08 |
| 6747501 | Dual-triggered electrostatic discharge protection circuit | Kei-Kang Hung, Hsin-Chin Jiang | 2004-06-08 |
| 6744107 | ESD protection circuit with self-triggered technique | Kuo-Chun Hsu, Wen-Yu Lo | 2004-06-01 |
| 6724592 | Substrate-triggering of ESD-protection device | Paul C. F. Tong, Ping Ping Xu, Kwong Shing Lin, Anna Tam | 2004-04-20 |
| 6717238 | Low-capacitance bonding pad for semiconductor device | Hsin-Chin Jiang | 2004-04-06 |
| 6690065 | Substrate-biased silicon diode for electrostatic discharge protection and fabrication method | Chyh-Yih Chang | 2004-02-10 |
| 6690067 | ESD protection circuit sustaining high ESD stress | Che-Hao Chuang, Hsin-Chin Jiang | 2004-02-10 |