Issued Patents 2004
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6785776 | DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism | Ravi Kumar Arimilli, Paul Umbarger | 2004-08-31 |
| 6782456 | Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism | Ravi Kumar Arimilli, Paul Umbarger | 2004-08-24 |
| 6687795 | Data processing system and method of communication that reduce latency of write transactions subject to retry | Ravi Kumar Arimilli, Paul Umbarger | 2004-02-03 |