Issued Patents 2004
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6813705 | Memory disambiguation scheme for partially redundant load removal | Evelyn Duesterwald, Vasanth Bala | 2004-11-02 |
| 6785801 | Secondary trace build from a cache of translations in a caching dynamic translator | Evelyn Duesterwald, Vasanth Bala | 2004-08-31 |
| 6725335 | Method and system for fast unlinking of a linked branch in a caching dynamic translator | Vasanth Bala, Evelyn Duesterwald | 2004-04-20 |