Issued Patents 2004
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6760266 | Sense amplifier and method for performing a read operation in a MRAM | Bradley J. Garni, Mark Deherrera, Mark Durlam, Bradley N. Engel, Joseph J. Nahas +1 more | 2004-07-06 |
| 6744663 | Circuit and method for reading a toggle memory cell | Brad J. Garni, Joseph J. Nahas, Chitra Subramanian | 2004-06-01 |
| 6714440 | Memory architecture with write circuitry and method therefor | Chitra Subramanian, Joseph J. Nahas | 2004-03-30 |
| 6711068 | Balanced load memory and method of operation | Chitra Subramanian, Brad J. Garni, Joseph J. Nahas, Halbert S. Lin | 2004-03-23 |
| 6711052 | Memory having a precharge circuit and method therefor | Chitra Subramanian, Joseph J. Nahas | 2004-03-23 |
| 6700814 | Sense amplifier bias circuit for a memory having at least two distinct resistance states | Joseph J. Nahas, Bradley J. Garni | 2004-03-02 |
| 6693824 | Circuit and method of writing a toggle memory | Joseph J. Nahas, Chitra Subramanian, Brad J. Garni | 2004-02-17 |