WD

Wei-Jin Dai

CS Cadence Design Systems: 3 patents #14 of 106Top 15%
📍 Cupertino, CA: #88 of 715 inventorsTop 15%
🗺 California: #2,168 of 28,370 inventorsTop 8%
Overall (2004): #18,381 of 270,089Top 7%
3
Patents 2004

Issued Patents 2004

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
6782519 Clock tree synthesis for mixed domain clocks Jui-Ming Chang, Chin-Chi Teng 2004-08-24
6782520 IC layout system having separate trial and detailed routing phases Mitsuru Igusa, Shiu-Ping Chao, Dennis Huang 2004-08-24
6751786 Clock tree synthesis for a hierarchically partitioned IC layout Chin-Chi Teng 2004-06-15