JS

Janardhana Swamy

CS Cadence Design Systems: 1 patents #23 of 106Top 25%
📍 San Jose, CA: #938 of 2,805 inventorsTop 35%
🗺 California: #8,555 of 28,370 inventorsTop 35%
Overall (2004): #198,600 of 270,089Top 75%
1
Patents 2004

Issued Patents 2004

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6686759 Techniques for testing embedded cores in multi-core integrated circuit designs — 2004-02-03