Issued Patents 2004
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6763503 | Accurate wire load model | Devendra Vidhani, Georgios Konstadinidis | 2004-07-13 |
| 6704911 | RC netlist reduction for timing and noise analysis | — | 2004-03-09 |
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6763503 | Accurate wire load model | Devendra Vidhani, Georgios Konstadinidis | 2004-07-13 |
| 6704911 | RC netlist reduction for timing and noise analysis | — | 2004-03-09 |