Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6665767 | Programmer initiated cache block operations | Sanjive Agarwala, Timothy David Anderson, Charles Fuoco | 2003-12-16 |
| 6658503 | Parallel transfer size calculation and annulment determination in transfer controller with hub and ports | Sanjive Agarwala, Iain Robertson | 2003-12-02 |
| 6654819 | External direct memory access processor interface to centralized transaction processor | Iain Robertson, Sanjive Agarwala | 2003-11-25 |
| 6629187 | Cache memory controlled by system address properties | Steven D. Krueger | 2003-09-30 |
| 6622181 | Timing window elimination in self-modifying direct memory access processors | Sanjive Agarwala | 2003-09-16 |
| 6606686 | Unified memory system architecture including cache and directly addressable static random access memory | Sanjive Agarwala, Charles Fuoco, Timothy David Anderson, Christopher L. Mobley | 2003-08-12 |
| 6594713 | Hub interface unit and application unit interfaces for expanded direct memory access processor | Charles Fuoco, Sanjive Agarwala, Raguram Damodaran | 2003-07-15 |
| 6594711 | Method and apparatus for operating one or more caches in conjunction with direct memory access controller | Timothy David Anderson, Sanjive Agarwala, Charles Fuoco | 2003-07-15 |
| 6574683 | External direct memory access processor implementation that includes a plurality of priority levels stored in request queue | Iain Robertson | 2003-06-03 |
| 6535958 | Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access | Charles Fuoco, Sanjive Agarwala, Timothy David Anderson, Christopher L. Mobley | 2003-03-18 |