Issued Patents 2003
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6642570 | Structure of flash memory with high coupling ratio | — | 2003-11-04 |
| 6638794 | Method for fabricating an anti-fuse in programmable interconnections | — | 2003-10-28 |
| 6627515 | Method of fabricating a non-floating body device with enhanced performance | Jyh-Chyurn Guo, Chenming Hu, Da-Chi Lin | 2003-09-30 |
| 6620687 | Method of making non-volatile memory with sharp corner | — | 2003-09-16 |
| 6620526 | Method of making a dual damascene when misalignment occurs | — | 2003-09-16 |
| 6596589 | Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer | — | 2003-07-22 |
| 6589840 | Nonvolatile memory device with reduced floating gate and increased coupling ratio and manufacturing method thereof | — | 2003-07-08 |
| 6576555 | Method of making upper conductive line in dual damascene having lower copper lines | — | 2003-06-10 |
| 6576537 | Flash memory cell and method for fabricating a flash memory cell | — | 2003-06-10 |
| 6548353 | Method of making nonvolatile memory device having reduced capacitance between floating gate and substrate | — | 2003-04-15 |
| 6537880 | Method of fabricating a high density NAND stacked gate flash memory device having narrow pitch isolation and large capacitance between control and floating gates | — | 2003-03-25 |
| 6531781 | Fabrication of transistor having elevated source-drain and metal silicide | — | 2003-03-11 |
| 6528402 | Dual salicidation process | — | 2003-03-04 |
| 6524939 | Dual salicidation process | — | 2003-02-25 |
| 6503764 | Method of making in high density DRAM circuit having a stacked capacitor | — | 2003-01-07 |