Issued Patents 2003
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6667509 | Method of forming sharp beak of poly by oxygen/fluorine implant to improve erase speed for split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hong-Cheng Sung | 2003-12-23 |
| 6635922 | Method to fabricate poly tip in split gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Jack Y. Yeh | 2003-10-21 |
| 6624025 | Method with trench source to increase the coupling of source to floating gate in split gate flash | Chia-Ta Hsieh, Chrong-Jun Lin, Wen-Ting Chu | 2003-09-23 |
| 6583466 | Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions | Chrong-Jung Lin, Shui-Hung Chen | 2003-06-24 |
| 6573555 | Source side injection programming and tip erasing P-channel split gate flash memory cell | Yai-Fen Lin, Hung-Cheng Sung, Chia-Ta Hsieh | 2003-06-03 |
| 6559501 | Method for forming split-gate flash cell for salicide and self-align contact | Hung-Cheng Sung, Chia-Ta Hsieh | 2003-05-06 |
| 6544828 | Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM | Wen-Ting Chu, Jack Y. Yeh, Chia-Ta Hsieh, Chrong-Jung Lin, Sheng-Wei Tsaur | 2003-04-08 |
| 6538277 | Split-gate flash cell | Hung-Cheng Sung, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu | 2003-03-25 |
| 6538276 | Split gate flash memory device with shrunken cell and source line array dimensions | Chia-Ta Hsieh, Yai-Fen Liu, Hung-Cheng Sung | 2003-03-25 |
| 6534821 | Structure with protruding source in split-gate flash | Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Wen-Ting Chu | 2003-03-18 |
| 6509603 | P-channel EEPROM and flash EEPROM devices | Yai-Fen Lin, Shiou-Hann Liaw, Juang-Ke Yeh | 2003-01-21 |
| 6504206 | Split gate flash cell for multiple storage | Hung-Cheng Sung, Chia-Ta Hsieh, Yai-Fen Lin | 2003-01-07 |