Issued Patents 2003
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6624015 | Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-09-23 |
| 6576517 | Method for obtaining a multi-level ROM in an EEPROM process flow | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-06-10 |
| 6573130 | Process for manufacturing electronic devices having non-salicidated non-volatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-06-03 |
| 6548857 | Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process | Bruno Vajana | 2003-04-15 |
| 6521957 | Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell | Matteo Patelmo, Nadia Galbiati, Bruno Vajana | 2003-02-18 |