RM

Robert G. Mathews

SD Sequence Design: 2 patents #1 of 13Top 8%
📍 Los Altos, CA: #104 of 436 inventorsTop 25%
🗺 California: #4,287 of 28,521 inventorsTop 20%
Overall (2003): #45,490 of 273,478Top 20%
2
Patents 2003

Issued Patents 2003

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6643831 Method and system for extraction of parasitic interconnect impedance including inductance Keh-Jeng Chang, Li-Fu Chang, Martin G. Walker 2003-11-04
6591407 Method and apparatus for interconnect-driven optimization of integrated circuit design Douglas Francis Kaufman, Hazem Almusa, Vinay Srinivas, Donald V. Organ, Larry Ke +2 more 2003-07-08