Issued Patents 2003
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6664588 | NROM cell with self-aligned programming and erasure areas | — | 2003-12-16 |
| 6649972 | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping | — | 2003-11-18 |
| 6643181 | Method for erasing a memory cell | Yair Sofer | 2003-11-04 |
| 6636440 | Method for operation of an EEPROM array, including refresh thereof | Eduardo Maayan, Ron Eliyahu, Shai Eisen | 2003-10-21 |
| 6633496 | Symmetric architecture for memory cells having widely spread metal bit lines | Eduardo Maayan | 2003-10-14 |
| 6633499 | Method for reducing voltage drops in symmetric array architectures | Eduardo Maayan | 2003-10-14 |
| 6627555 | Method and circuit for minimizing the charging effect during manufacture of semiconductor devices | Ilan Bloom | 2003-09-30 |
| 6614692 | EEPROM array and method for operation thereof | Ron Eliyahu, Eduardo Maayan, Ilan Bloom | 2003-09-02 |
| 6584017 | Method for programming a reference cell | Eduardo Maayan, Ron Eliyahu, Ameet Lann | 2003-06-24 |
| 6583007 | Reducing secondary injection effects | — | 2003-06-24 |
| 6566699 | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping | — | 2003-05-20 |
| 6552387 | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping | — | 2003-04-22 |
| 6535434 | Architecture and scheme for a non-strobed read sequence | Eduardo Maayan, Yair Sofer, Ron Eliyahu | 2003-03-18 |