Issued Patents 2003
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6665206 | Array architecture for depletion mode ferroelectric memory devices | — | 2003-12-16 |
| 6646906 | Methods of reading ferroelectric memory cells | — | 2003-11-11 |
| 6627955 | Structure and method of MOS transistor having increased substrate resistance | Zhiqiang Wu, Che-Jen Hu | 2003-09-30 |
| 6587365 | Array architecture for depletion mode ferroelectric memory devices | — | 2003-07-01 |
| 6574131 | Depletion mode ferroelectric memory device and method of writing to and reading from the same | — | 2003-06-03 |
| 6563175 | NMOS ESD protection device with thin silicide and methods for making same | Wei-Tsun Shiau, Jerry Hu | 2003-05-13 |
| 6522571 | Methods of forming and reading ferroelectric memory cells | — | 2003-02-18 |
| 6515889 | Junction-isolated depletion mode ferroelectric memory | Brian W. Huber | 2003-02-04 |