Issued Patents 2003
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6649480 | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs | Nicole Gerrish | 2003-11-18 |
| 6646322 | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits | — | 2003-11-11 |
| 6602613 | Heterointegration of materials using deposition and bonding | — | 2003-08-05 |
| 6593191 | Buried channel strained silicon FET using a supply layer created through ion implantation | — | 2003-07-15 |
| 6594293 | Relaxed InxGa1-xAs layers integrated with Si | Mayank Bulsara | 2003-07-15 |
| 6589335 | Relaxed InxGa1-xAs layers integrated with Si | Mayank Bulsara | 2003-07-08 |
| 6583015 | Gate technology for strained surface channel and strained buried channel MOSFET devices | Richard Hammond, Matthew T. Currie | 2003-06-24 |
| 6573126 | Process for producing semiconductor article using graded epitaxial growth | Zhi-Yuan Cheng, Dimitri Antoniadis, Judy L. Hoyt | 2003-06-03 |
| 6555839 | Buried channel strained silicon FET using a supply layer created through ion implantation | — | 2003-04-29 |
| 6521041 | Etch stop layer system | Kenneth Chai-en Wu, Jeffrey T. Borenstein | 2003-02-18 |
| 6518644 | Low threading dislocation density relaxed mismatched epilayers without high temperature growth | — | 2003-02-11 |
| 6503773 | Low threading dislocation density relaxed mismatched epilayers without high temperature growth | — | 2003-01-07 |