Issued Patents 2003
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6671839 | Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith | Benoit Nadeau-Dostie | 2003-12-30 |
| 6614263 | Method and circuitry for controlling clocks of embedded blocks during logic bist test mode | Benoit Nadeau-Dostie | 2003-09-02 |
| 6615392 | Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby | Benoit Nadeau-Dostie, Dwayne Burek, Sonny Ngai San Shum, Pierre Girouard, Pierre Gauther +3 more | 2003-09-02 |
| 6536008 | Fault insertion method, boundary scan cells, and integrated circuit for use therewith | Benoit Nadeau-Dostie, Pierre Gauthier | 2003-03-18 |
| 6510534 | Method and apparatus for testing high performance circuits | Benoit Nadeau-Dostie, Fadi Maamari, Dwayne Burek | 2003-01-21 |