HS

Hirofumi Saito

NE Nec Electronics: 2 patents #25 of 322Top 8%
NE Nec: 1 patents #355 of 1,409Top 30%
📍 Takizawa, CA: #1 of 1 inventorsTop 100%
Overall (2003): #29,542 of 273,478Top 15%
3
Patents 2003

Issued Patents 2003

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
6617669 Multilayer semiconductor wiring structure with reduced alignment mark area — 2003-09-09
6589718 Method of making resist pattern — 2003-07-08
6514851 Method of fabrication of multilayer semiconductor wiring structure with reduced alignment mark area — 2003-02-04