Issued Patents 2003
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6647464 | System and method utilizing speculative cache access for improved performance | Dean Mulla, Tom Grutkowski | 2003-11-11 |
| 6583650 | Latching annihilation based logic gate | Samuel D. Naffziger, Jayen Desai | 2003-06-24 |
| 6557078 | Cache chain structure to implement high bandwidth low latency cache memory subsystem | Dean Mulla, Terry L Lyon, Thomas Grutkowski | 2003-04-29 |
| 6550034 | Built-in self test for content addressable memory | Donald R. Weiss | 2003-04-15 |
| 6539466 | System and method for TLB buddy entry self-timing | — | 2003-03-25 |
| 6539457 | Cache address conflict mechanism without store buffers | Dean Mulla, Thomas Grutkowski | 2003-03-25 |
| 6507892 | L1 cache memory | Dean Mulla, Terry L Lyon, Tom Grutkowski | 2003-01-14 |