Issued Patents 2003
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6633190 | Multi-phase clock generation and synchronization | Atila Alvandpour, Daniel Eckerbert | 2003-10-14 |
| 6628557 | Leakage-tolerant memory arrangements | Steven Hsu | 2003-09-30 |
| 6628143 | Full-swing source-follower leakage tolerant dynamic logic | Steven Hsu, Mark A. Anders, Sanu K. Mathew | 2003-09-30 |
| 6617892 | Single ended interconnect systems | Krishnamurthy Soumyanath | 2003-09-09 |
| 6618316 | Pseudo-static single-ended cache cell | Steven Hsu | 2003-09-09 |
| 6614279 | Clock receiver circuit for on-die salphasic clocking | Mark A. Anders, Krishnamurthy Soumyanath | 2003-09-02 |
| 6614680 | Current leakage reduction for loaded bit-lines in on-chip memory structures | Atila Alvandpour, Siva G. Narendra | 2003-09-02 |
| 6600340 | Noise tolerant wide-fanin domino circuits | Lei Wang, Rajamohana Hegde | 2003-07-29 |
| 6597623 | Low power architecture for register files | Ganesh Balamurugan | 2003-07-22 |
| 6590801 | Current leakage reduction for loaded bit-lines in on-chip memory structures | Atila Alvandpour, Siva G. Narendra | 2003-07-08 |
| 6573756 | Active noise-canceling scheme for dynamic circuits | Sanu K. Mathew, Mark A. Anders | 2003-06-03 |
| 6571269 | Noise-tolerant digital adder circuit and method | Jay Anderson | 2003-05-27 |
| 6563357 | Level converting latch | Steven Hsu, Bhaskar P. Chatterjee | 2003-05-13 |
| 6549040 | Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates | Atila Alvandpour, Krishnamurthy Soumyanath | 2003-04-15 |
| 6519178 | Current leakage reduction for loaded bit-lines in on-chip memory structures | Atila Alvandpour, Siva G. Narendra | 2003-02-11 |
| 6510092 | Robust shadow bitline circuit technique for high-performance register files | Sanu K. Mathew | 2003-01-21 |
| 6510077 | Current leakage reduction for loaded bit-lines in on-chip memory structures | Atila Alvandpour, Siva G. Narendra | 2003-01-21 |