Issued Patents 2003
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670654 | Silicon germanium heterojunction bipolar transistor with carbon incorporation | Louis D. Lanzerotti, Brian P. Ronan | 2003-12-30 |
| 6635548 | Capacitor and method for forming same | Kerry Bernstein, Nicholas Theodore Schmidt, Anthony K. Stamper, Stephen A. St. Onge | 2003-10-21 |
| 6628159 | SOI voltage-tolerant body-coupled pass transistor | — | 2003-09-30 |
| 6600199 | Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity | Robb Johnson, Louis D. Lanzerotti, Stephen A. St. Onge | 2003-07-29 |
| 6586818 | Self-aligned silicon germanium heterojunction bipolar transistor device with electrostatic discharge crevice cover for salicide displacement | — | 2003-07-01 |
| 6574078 | Method and apparatus for providing electrostatic discharge protection of a magnetic head using a mechanical switch and an electrostatic discharge device network | — | 2003-06-03 |
| 6563176 | Asymmetrical semiconductor device for ESD protection | Robert J. Gauthier, Jr. | 2003-05-13 |
| 6552406 | SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks | — | 2003-04-22 |
| 6552879 | Variable voltage threshold ESD protection | — | 2003-04-22 |
| 6549061 | Electrostatic discharge power clamp circuit | Alan B. Botula, David Hui | 2003-04-15 |
| 6548338 | Integrated high-performance decoupling capacitor and heat sink | Kerry Bernstein, Robert M. Geffken, Wilbur D. Pricer, Anthony K. Stamper | 2003-04-15 |
| 6531741 | Dual buried oxide film SOI structure and method of manufacturing the same | Michael Hargrove | 2003-03-11 |
| 6526548 | Method for evaluating circuit design for ESD electrostatic discharge robustness | — | 2003-02-25 |
| 6512296 | Semiconductor structure having heterogenous silicide regions having titanium and molybdenum | Robert J. Gauthier, Jr., Randy W. Mann | 2003-01-28 |