Issued Patents 2003
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6631502 | Method of analyzing integrated circuit power distribution in chips containing voltage islands | Joseph N. Kozhaya, Paul D. Montane, Robert A. Proctor, Erich C. Schanzenbach, Ivan L. Wemple | 2003-10-07 |
| 6606732 | Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages | Craig Lussier, Joseph Natonio | 2003-08-12 |
| 6586828 | Integrated circuit bus grid having wires with pre-selected variable widths | Yu Sun | 2003-07-01 |
| 6584596 | Method of designing a voltage partitioned solder-bump package | Charles S. Chiu, Yu Sun | 2003-06-24 |
| 6538314 | Power grid wiring for semiconductor devices having voltage islands | Yu Sun | 2003-03-25 |
| 6523150 | Method of designing a voltage partitioned wirebond package | Charles S. Chiu, Yu Sun | 2003-02-18 |