Issued Patents 2003
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6660585 | Stacked gate flash memory cell with reduced disturb conditions | Peter Wung Lee, Hsing-Ya Tsao, Vei-Han Chan, Hung-Sheng Chen | 2003-12-09 |
| 6628563 | Flash memory array for multiple simultaneous operations | Peter Wung Lee, Hsing-Ya Tsao | 2003-09-30 |
| 6620682 | Set of three level concurrent word line bias conditions for a nor type flash memory array | Peter Wung Lee, Hsing-Ya Tsao, Mervyn Wong | 2003-09-16 |
| 6584034 | Flash memory array structure suitable for multiple simultaneous operations | Peter Wung Lee, Hsing-Ya Tsao | 2003-06-24 |
| 6574152 | Circuit design for accepting multiple input voltages for flash EEPROM memory operations | Peter Wung Lee, Hsing-Ya Tsao | 2003-06-03 |
| 6556481 | 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell | Hsing-Ya Tsao, Peter Wung Lee, Mervyn Wong | 2003-04-29 |
| 6515910 | Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM | Peter Wung Lee, Hsing-Ya Tsao, Tam Tran | 2003-02-04 |